1. Field of the Invention
The present invention relates to a logic circuit in a semiconductor integrated circuit, more particularly relates to a logic circuit for generating an exclusive-OR (EXOR=A(+)B) and a dual signal thereof (EXNOR=A{circumflex over ( )}(+)B) at almost the same time, and a full adder using the same.
2. Description of the Related Art
8tr Type EXOR and EXNOR Logic Circuits
Conventionally, and also at present, the circuit shown in FIG. 1 has been generally frequently used as an EXOR logic circuit, and the circuit shown in FIG. 2 has been generally frequently used as an EXNOR logic circuit (refer to for example John P. Uyemura, xe2x80x9cCMOS LOGIC CIRCUIT DESIGNxe2x80x9d, Kluwer Academic Publishers, 1999, pp. 274 to pp. 275, FIG. 6.21 to 6.22).
An EXOR logic circuit 1 of FIG. 1 comprises two CMOS transmission gates TMG11 and TMG12 and two CMOS inverters INV11 and INV12 and is configured by eight transistors in total.
In this EXOR logic circuit 1, an input terminal TIN11 of a logic signal A is connected to an input terminal of an inverter INV11, a gate of a p-channel MOS (PMOS) transistor of the transmission gate TMG11, and a gate of an n-channel MOS (NMOS) transistor of the transmission gate TMG12.
An output terminal of the inverter INV11 is connected to a gate of the NMOS transistor of the transmission gate TMG11 and a gate of the PMOS transistor of the transmission gate TMG12.
Further, an input terminal TIN12 of a logic signal B is connected to an input terminal of the inverter INV12 and one input/output terminal of the transmission gate TMG11, while an output terminal of the inverter INV12 is connected to one input/output terminal of the transmission gate TMG12.
The other input/output terminals of the transmission gates TMG11 and TMG12 are commonly connected to an output terminal TOT11 of an exclusive-OR A(+)B.
Similarly, an EXNOR logic circuit 2 of FIG. 2 comprises two CMOS transmission gates TMG21 and TMG22 and two CMOS inverters INV21 and INV22 and is configured by eight transistors in total.
In this EXOR logic circuit 2, an input terminal TIN21 of the logic signal A is connected to the input terminal of an inverter INV21, a gate of the PMOS transistor of the transmission gate TMG21, and a gate of the NMOS transistor of the transmission gate TMG22.
An output terminal of the inverter INV21 is connected to a gate of the NMOS transistor of the transmission gate TMG21 and a gate of the PMOS transistor of the transmission gate TMG22.
Further, an input terminal TIN22 of the logic signal B is connected to an input terminal of the inverter INV22 and one input/output terminal of the transmission gate TMG22, while an output terminal of the inverter INV22 is connected to one input/output terminal of the transmission gate TMG21.
The other input/output terminals of the transmission gates TMG21 and TMG22 are commonly connected to an output terminal TOT21 of a dual signal A{circumflex over ( )}(+)B of the exclusive-OR A(+)B.
6tr Type EXOR and EXNOR Logic Circuits
Further, as an improvement of the 8tr type, there are 6tr type EXOR and EXNOR logic circuits as shown in FIG. 3 and FIG. 4 (refer to for example John P. Uyemura, xe2x80x9cCMOS LOGIC CIRCUIT DESIGNxe2x80x9d, Kluwer Academic Publishers, 1999, pp. 275, FIG. 6.23).
The 6tr type EXOR circuit 3 shown in FIG. 3 comprises a PMOS transistor PT31, an NMOS transistor NT31, a transmission gate TMG31, and an inverter INV31 and is configured by six transistors in total.
An input terminal TIN31 of the logic signal A is connected to the gates of the PMOS transistor PT31 and the NMOS transistor TN31 and one input/output terminal of the transmission gate TMG31.
An input terminal TIN32 of the logic signal B is connected to a source of the PMOS transistor PT31 and an input terminal of the inverter INV31, while an output terminal of the inverter INV31 is connected to a source of the NMOS transistor NT31.
The drains of the PMOS transistor PT31 and the NMOS transistor NT31 and the other input/output terminal of the transmission gate TMG31 are commonly connected to an output terminal TOT31 of the exclusive-OR A(+)B.
Similarly, the 6tr type EXNOR circuit 4 shown in FIG. 4 comprises a PMOS transistor PT41, an NMOS transistor NT41, a transmission gate TMG41, and an inverter INV41 and is configured by six transistors in total.
An input terminal TIN41 of the logic signal A is connected to the gates of the PMOS transistor PT41 and the NMOS transistor TN41 and one input/output terminal of the transmission gate TMG41.
An input terminal TIN42 of the logic signal B is connected to a source of the NMOS transistor NT41 and an input terminal of the inverter INV41, while an output terminal of the inverter INV41 is connected to a source of the PMOS transistor PT41.
The drains of the PMOS transistor PT41 and the NMOS transistor NT41 and the other input/output terminal of the transmission gate TMG41 are commonly connected to an output terminal TOT41 of the dual signal A{circumflex over ( )}(+)B of the exclusive-OR A(+)B.
These 6tr type EXOR logic circuit 3 and EXNOR logic circuit 4 are decreased in the number of transistors by two from the 8tr type logic circuits shown in FIG. 1 and FIG. 2 and are excellent in the points of area efficiency and power consumption in comparison with those of the 8tr type.
4tr Type EXOR and EXNOR Logic Circuits
Further, there are 4tr type EXOR and EXNOR logic circuits configured by four transistors as shown in FIG. 5 and FIG. 6 (refer to for example John P. Uyemura, xe2x80x9cCMOS LOGIC CIRCUIT DESIGNxe2x80x9d, Kluwer Academic Publishers, 1999, pp. 256, FIG. 5.79).
The 4tr type EXOR circuit 5 shown in FIG. 5 comprises PMOS transistors PT51 and PT52 and NMOS transistors NT51 and NT52 and is configured by four transistors in total.
The PMOS transistor PT51 is connected between an input terminal TINS1 of the logic signal A and an output terminal TOT51 of the exclusive-OR A(+)B, while the PMOS transistor PT52 is connected between an input terminal TIN52 of the logic signal B and the output terminal TOT51.
Further, the NMOS transistors NT51 and NT52 are connected in series between the output terminal TOT51 and a ground GND.
The gate of the PMOS transistor PT52 and the gate of the NMOS transistor NT51 are connected to the input terminal TIN51, while the gate of the PMOS transistor PT51 and the gate of the NMOS transistor NT52 are connected to the input terminal TIN52.
Similarly, the 4tr type EXNOR circuit 6 shown in FIG. 6 comprises PMOS transistors PT61 and PT62 and NMOS transistors NT61 and NT62 and is configured by four transistors in total.
The NMOS transistor NT61 is connected between an input terminal TIN61 of the logic signal A and an output terminal TOT61 of the dual signal A{circumflex over ( )}(+)B of the exclusive-OR A(+)B, while the NMOS transistor NT62 is connected between an input terminal TIN62 of the logic signal B and the output terminal TOT61.
Further, the PMOS transistors PT61 and PT62 are connected in series between a supply line of a power supply voltage VDD and the output terminal TOT61.
The gate of the PMOS transistor PT62 and the gate of the NMOS transistor NT62 are connected to the input terminal TIN61, while the gate of the PMOS transistor PT61 and the gate of the NMOS transistor NT61 are connected to the input terminal TIN62.
As one element circuit frequently used in a processor in an integrated circuit, there is a full adder.
FIG. 7 is a circuit diagram of an example of the configuration of a generation circuit of a carry signal CO of a full adder.
This carry signal generation circuit 7 is configured by an EXOR logic circuit 71, transmission gates TMG71 and TMG72, and an inverter INV71.
An input terminal TIN71 of the logic signal A is connected to one input terminal of the EXOR logic circuit 71 and one input/output terminal of the transmission gate TMG71, while an input terminal TIN72 of the logic signal B is connected to the other input terminal of the EXOR logic circuit 71. Further, an input terminal TIN73 of the carry signal C is connected to one input/output terminal of a transmission gate TMG72.
Further, an output terminal of the EXOR logic circuit 71 is connected to an input terminal of the inverter INV71, a gate of the PMOS transistor of the transmission gate TMG71, and a gate of the NMOS transistor of the transmission gate TMG72.
An output terminal of the inverter INV71 is connected to a gate of the NMOS transistor of the transmission gate TMG71 and a gate of the PMOS transistor of the transmission gate TMG72.
The other input/output terminals of the transmission gates TMG71 and TMG72 are commonly connected to the output terminal TOT71 of the carry signal CO.
The carry signal generation logic described in textbooks and the like is CO=Axc2x7B+Bxc2x7C+Cxc2x7A, but generally is realized as CO=(A{circumflex over ( )}(+)B)xc2x7A+(A(+)B)xc2x7C by commonly using A(+)B which becomes necessary for generating a sum signal S=A(+)B(+)C (refer to for example John P. Uyemura, xe2x80x9cCMOS LOGIC CIRCUIT DESIGNxe2x80x9d, Kluwer Academic Publishers, 1999, pp. 276 to pp. 277, equation (6.45), FIG. 6.25).
The A{circumflex over ( )}(+)B necessary for the generation of the carry signal CO is obtained by inversion of the exclusive-OR A(+)B. At this time, due to the delay of one inverter, a phase difference occurs between the signals A(+)B and A{circumflex over ( )}(+)B.
This situation is shown more generalized in FIGS. 8A and 8B.
Since there is a phase difference between a signal S and an inverted signal {circumflex over ( )}S thereof, the point at which the two signals intersect is not on a center value of the amplitude.
When the intersecting point is at a potential lower than the center value, it is determined that both S1 and {circumflex over ( )}S have a logic value xe2x80x9c0xe2x80x9d in terms of the logic circuit. Similarly, when the intersecting point is at a potential higher than the center value, it is determined that the two are xe2x80x9c1xe2x80x9d.
Under the situation where S={circumflex over ( )}S, both of the two selectors configured by two CMOS transmission gates become ON.
When the two input signals are different from each other at this time, a logic collision occurs, there is an electrical short-circuit, and a current flows. Such a phenomenon is generally known as xe2x80x9cwraparound of the signalxe2x80x9d.
FIG. 9 and FIG. 10 are diagrams of the results of simulation in the cases of conventional 8tr type and 6tr type EXOR logic circuits having inverters for inverting the input signals and passing the outputs thereof through one inverter.
As apparent from the diagrams, in the conventional 8tr type and 6tr type EXOR logic circuits, phase differences arise between the two outputs and therefore the intersecting points are not at the center values of the amplitudes.
Further, although the 4tr type EXOR and EXNOR logic circuits each configured by four transistors may, at first glance, seem superior to the 6tr type logic circuit, in actuality they are not superior.
In FIG. 5, when A=0 and B=0, the two PMOS transistors PT51 and PT52 become ON, and a logic potential xe2x80x9c0xe2x80x9d is transferred to the output through the two PMOS transistors PT51 and PT52.
However, the PMOS transistors PT51 and PT52 cannot completely transfer the logic potential xe2x80x9c0xe2x80x9d and therefore a potential which has become higher by the amount of the threshold value of the PMOS transistors appears at the output.
On the other hand, in FIG. 6, when A=1 and B=1, the two PMOS transistors PT61 and PT62 cut off, the two NMOS transistors NT61 and NT62 become ON, and a logic potential xe2x80x9c1xe2x80x9d is transferred to the output through the two NMOS transistors NT61 and NT62.
However, the NMOS transistors NT61 and NT62 cannot completely transfer the logic potential xe2x80x9c1xe2x80x9d and therefore a potential which has become lower by the amount of the threshold value of the NMOS transistors appears at the output.
Signals of such incomplete logic potentials exert a serious influence upon a low voltage operation margin and noise margin. For this reason, in actuality, it is necessary to provide and use inverters INV51 and INV61 as buffers for restoration of the potential as shown in FIG. 11 and FIG. 12.
The present invention was made in consideration with such a circumstance and has as an object thereof to provide a logic circuit capable of suppressing an occurrence of wraparound of a signal, capable of reducing the power consumption, and achieving a reduction of circuit scale and an improvement of operating speed and a full adder using the same.
According to a first aspect of the present invention, there is provided a logic circuit, comprising an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal, a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and an interpolation circuit for compulsorily setting an output level of said dual signal at the first level when the output level of said exclusive-OR is the second level.
According to a second aspect of the present invention, there is provided a logic circuit, comprising an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal, a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and an interpolation circuit for compulsorily setting the output level of said exclusive-OR at the second level when the output level of said dual signal is the first level.
According to a third aspect of the present invention, there is provided a logic circuit, comprising an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal, a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and an interpolation circuit for compulsorily setting an output level of said dual signal at the first level when the output level of said exclusive-OR is the second level, while compulsorily setting the output level of said exclusive-OR at the second level when the output level of said dual signal is the first level.
According to a fourth aspect of the present invention, there is provided a logic circuit, comprising a first input terminal with a first logic signal taking a first or second level input thereto; a second input terminal with a second logic signal taking a first or second level input thereto; a first output terminal for outputting an exclusive-OR; a second output terminal for outputting a dual signal of said exclusive-OR; a dual signal generation circuit having first conductivity type first and second transistors connected in series between said first level use power supply potential and said second output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, a second conductivity type first transistor connected between said first input terminal and said second output terminal, turning ON when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, and a second conductivity type second transistor connected between said second input terminal and said second output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied; an exclusive-OR generation circuit having a first conductivity type third transistor connected between said first input terminal and said first output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, a first conductivity type fourth transistor connected between said second input terminal and said first output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and second conductivity type third and fourth transistors connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied; and an interpolation circuit having a first conductivity type fifth transistor connected in series between said first level use power supply potential and said second output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and a second conductivity type fifth transistor connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, wherein the control terminals of said first conductivity type second and fourth transistors and second conductivity type second and third transistors are connected to said first input terminal; the control terminals of said first conductivity type first and third transistors and second conductivity type first and fourth transistors are connected to said second input terminal; the control terminal of said first conductivity type fifth transistor is connected to said first output terminal; and the control terminal of said second. conductivity type fifth transistor is connected to said second output terminal.
According to a fifth aspect of the present invention, there is provided a full adder, comprising a logic circuit having an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal, a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and an interpolation circuit for compulsorily setting an output level of said dual signal at the first level when the output level of said exclusive-OR is the second level, a sum signal generation circuit for generating a sum signal based on an exclusive-OR output and a dual signal output of said logic circuit, and a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.
According to a sixth aspect of the present invention, there is provided a full adder, comprising a logic circuit having an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal, a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and an interpolation circuit for compulsorily setting the output level of said exclusive-OR at the second level when the output level of said dual signal is the first level; a sum signal generation circuit for generating a sum signal based on the exclusive-OR output and the dual signal output of said logic circuit; and a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.
According to a seventh aspect of the present invention, there is provided a full adder, comprising a logic circuit having an exclusive-OR generation circuit for receiving a first logic signal and a second logic signal taking a first or second level and generating an exclusive-OR of the first logic signal and second logic signal, a dual signal generation circuit for receiving the first logic signal and the second logic signal taking the first or second level and generating a dual signal of the exclusive-OR of the first logic signal and second logic signal, and an interpolation circuit for compulsorily setting an output level of said dual signal at the first level when the output level of said exclusive-OR is the second level, while compulsorily setting the output level of said exclusive-OR at the second level when the output level of said dual signal is the first level; a sum signal generation circuit for generating a sum signal based on an exclusive-OR output and a dual signal output of said logic circuit; and a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.
According to a eighth aspect of the present invention, there is provided a full adder, comprising a logic circuit having a first input terminal with a first logic signal taking a first or second level input thereto, a second input terminal with a second logic signal taking a first or second level input thereto, a first output terminal for outputting an exclusive-OR, a second output terminal for outputting a dual signal of said exclusive-OR, a dual signal generation circuit which has first conductivity type first and second transistors connected in series between said first level use power supply potential and said second output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, a second conductivity type first transistor connected between said first input terminal and said second output terminal, turning ON when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, and a second conductivity type second transistor connected between said second input terminal and said second output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, an exclusive-OR generation circuit which has a first conductivity type third transistor connected between said first input terminal and said first output terminal, turning ON when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, a first conductivity type fourth transistor connected between said second input terminal and said first output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and second conductivity type third and fourth transistors connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, and an interpolation circuit which has a first conductivity type fifth transistor connected in series between said first level use power supply potential and said second output terminal, turning on when the signal of second level is supplied to the control terminal, while cutting off when the signal of first level is supplied, and a second conductivity type fifth transistor connected in series between said second level use power supply potential and said first output terminal, turning on when the signal of first level is supplied to the control terminal, while cutting off when the signal of second level is supplied, wherein the control terminals of said first conductivity type second and fourth transistors and second conductivity type second and third transistors are connected to said first input terminal, the control terminals of said first conductivity type first and third transistors and second conductivity type first and fourth transistors are connected to said second input terminal, the control terminal of said first conductivity type fifth transistor is connected to said first output terminal, and the control terminal of said second conductivity type fifth transistor is connected to said second output terminal; a sum signal generation circuit for generating a sum signal based on an exclusive-OR output and a dual signal output of said logic circuit; and a carry signal generation circuit for generating a carry signal by selecting said first logic signal or carry signal based on the exclusive-OR output and the dual signal output of said logic circuit.
Further, in the present invention, said first conductivity type first, second, third, fourth, and fifth transistors are p-channel field effect transistors, and said second conductivity type first, second, third, fourth, and fifth transistors are n-channel field effect transistors.
According to the logic circuit of the present invention, the exclusive-OR (EXOR=A(+)B) and the dual signal thereof (EXNOR=A{circumflex over ( )}(+)B) are approximately simultaneously generated without generating an inversion of the two first and second input logic signals A and B.
At this time, in accordance with for example the level of the input signal, when the output level of the exclusive-OR is the second level, the output level of the dual signal is compulsorily set at the first level by the interpolation circuit.
Further, when the output level of the dual signal is the first level, the output level of the exclusive-OR is compulsorily set at the second level.
Further, according to the full adder of the present invention, the dual signal is generated in the logic circuit and supplied to the carry signal generation circuit.
Accordingly, an inverter for inverting the logic as in the conventional circuit is unnecessary. As a result, the occurrence of wraparound of the signal is suppressed.